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[VHDL-FPGA-Verilog] sdram_vhd_134

Description: Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
Platform: | Size: 54272 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[VHDL-FPGA-Verilog] dualporttst-1_0

Description: xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
Platform: | Size: 195584 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[VHDL-FPGA-Verilog] BlockRAM

Description: xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
Platform: | Size: 2048 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[VHDL-FPGA-Verilog] TechXclusives-ReconfiguringBlockRAMs

Description: Xilinx FPGA block RAM reconfig via JTAG
Platform: | Size: 104448 | Author: Kraja | Hits:

[VHDL-FPGA-Verilog] dpRam1

Description: Dual port ram design project developed in Xilinx using VHDL
Platform: | Size: 741376 | Author: qaziguy | Hits:

[Other] jj

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Platform: | Size: 546816 | Author: 黄奇家 | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta

Description: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Platform: | Size: 16619520 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] lab5

Description: m*n的ram，包含m*n个ram，使用VHDL编译，可在xilinx里面运行-m* n the ram, contains m* n a ram, using the VHDL compiler, which can be run in xilinx
Platform: | Size: 22528 | Author: gao | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:

[VHDL-FPGA-Verilog] dpram

Description: FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
Platform: | Size: 352256 | Author: hzh | Hits:

[VHDL-FPGA-Verilog] Package

Description: Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation-Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation
Platform: | Size: 4604928 | Author: Sharav | Hits:

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